Integrated circuits (IC) are fabricated on a wafer in parallel. After processing, the wafer is diced to singulate the dies into individual chips. As part of processing the ICs, seal rings are formed in the back-end-of-line (BEOL) dielectric. A seal ring surrounds an IC to protect the IC from damage by saw-induced cracks propagating into the IC as well as moisture absorption.
However, conventional seal ring designs lead to defects from packaging of the IC. For example, resist bubbles are formed at corners of the seal ring. This causes defects in the packaging process, such as under-bump due to poor seed layer coverage.
The present disclosure is directed to ICs with an improved seal ring design for semiconductor devices.